1. Technical Field
The present invention relates to memory devices in general, and in particular to chalcogenide memory devices. Still more particularly, the present invention relates to a non-volatile single-event upset tolerant latch circuit.
2. Description of Related Art
In certain environments, such as satellite orbital space, in which the level of radiation is relatively intense, memory devices, such as static random access memories (SRAMs), are more susceptible to single-event upsets (SEUs) or soft errors than they would have in terrestrial environments. These SEUs are typically caused by electron-hole pairs created by, and travelling along the path of, a single energetic particle as it passes through the memory cells of the SRAMs. Should the energetic particle generate a critical charge within a storage node of an SRAM cell, the logic state of the SRAM cell will be upset. By the same token, other circuits used in conjunction with SRAMs are also susceptible to SEUs.
In the existing re-programmable SRAM-based field programmable gate arrays (FPGAs), a device configuration is typically stored in the volatile SRAM cells and must be reloaded at each power-up. Non-volatile FPGAs having flash memories can be utilized to store device configurations, but the flash memory cells are not radiation tolerant either, and there are reliability limitations for flash memory cells.